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mos integrated circuit m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y v850/sv1 tm 32-/16-bit single-chip microcontrollers preliminary data sheet document no. u13953ej1v0ds00 (1st edition) date published march 2000 n cp(k) printed in japan the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. not all devices/types available in every country. please check with local nec representative for availability and additional information. description the m pd703039, 703039y, 703040, 703040y, 703041, and 703041y (collectively known as the v850/sv1) are products in the low-power series of v850 family tm products, which are necs single-chip microcontrollers for real- time control. the v850/sv1 employs the cpu core of the v850 family, and has on-chip peripheral functions such as large capacity rom/ram, a multi-function timer/counter, serial interface, a/d converter, dma controller, pwm, and a vsync/hsync separation circuit. the v850/sv1 not only realizes the low power consumption necessary for applications such as camcorders, but also extremely high cost performance. detailed function descriptions are provided in the following users manuals. be sure to read them before designing. v850/sv1 users manual hardware : u14462e v850 family users manual architecture : u10243e features { number of instructions: 74 { minimum instruction execution time: 62.5 ns (@ 16 mhz operation with main system clock) 30.5 m s (@ 32.768 khz operation with subsystem clock) { general-purpose registers: 32 bits 32 registers { instruction set (signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions) { memory space: 16 mb linear address space memory block allocation function: 2 mb per block { external bus: 16-bit multiplexed bus { internal memory: m pd703039, 703039y (rom: 256 kb, ram: 8 kb) m pd703040, 703040y (rom: 256 kb, ram: 16 kb) m pd703041, 703041y (rom: 192 kb, ram: 8 kb) { i/o lines total: 151 { 10-bit resolution a/d converter: 16 channels { timer/counter 24-bit: 2 channels, 16-bit: 2 channels 8-bit: 8 channels { watch timer: 1 channel { watchdog timer: 1 channel { dma controller: 6 channels { interrupts and exceptions non-maskable interrupt: 2 sources maskable interrupt : m pd703039, 703040, 703041 (51 sources) : m pd703039y, 703040y, 703041y (52 sources) software exception: 32 sources exception trap: 1 source { serial interface (sio) asynchronous serial interface (uart) clocked serial interface (csi) 3-wire variable length serial interface (csi4) i 2 c bus interface (i 2 c) ( m pd703039y, 703040y, 703041y) { rtp: 8 bits 2 channels or 4 bits 4 channels the mark shows major revised points. ? 2000
preliminary data sheet u13953ej1v0ds00 2 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y { pwm output: 4 channels { vsync/hsync separation circuit { on-chip key return function { on-chip clock generator { power saving function: halt/idle/stop modes { rom correction: 4 points changeable { package: 176-pin plastic lqfp (24 24 mm) applications { system/servo/camera control of camcorders { portable cameras such as digital still cameras { cellular phones, portable information terminals, etc. ordering information part number package m pd703039gm- -ueu m pd703039ygm- -ueu m pd703040gm- -ueu m pd703040ygm- -ueu m pd703041gm- -ueu m pd703041ygm- -ueu 176-pin plastic lqfp (fine pitch) (24 24 mm) 176-pin plastic lqfp (fine pitch) (24 24 mm) 176-pin plastic lqfp (fine pitch) (24 24 mm) 176-pin plastic lqfp (fine pitch) (24 24 mm) 176-pin plastic lqfp (fine pitch) (24 24 mm) 176-pin plastic lqfp (fine pitch) (24 24 mm) remark indicates rom code suffix. differences between v850/sv1 products internal rom internal ram i 2 cv pp pin m pd703039 none m pd703039y 8 kb provided m pd703040 none m pd703040y 256 kb (mask rom) 16 kb provided m pd703041 none m pd703041y 192 kb (mask rom) 8 kb provided none m pd70f3040 none m pd70f3040y 256 kb (flash memory) 16 kb provided provided
preliminary data sheet u13953ej1v0ds00 3 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y pin configuration 176-pin plastic lqfp (fine pitch) (24 24 mm) m pd703039gm- -ueu m pd703039ygm- -ueu m pd703040gm- -ueu m pd703040ygm- -ueu m pd703041gm- -ueu m pd703041ygm- -ueu 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 p87/ani15 p86/ani14 p85/ani13 p84/ani12 p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 p147 p146 p145/rtptrg1 p144/ti9/intti9 p143/intcp93 p142/intcp92 p141/intcp91 p140/intcp90 p137/to81 p136/to80 p135/tclr8/inttclr8 p134/ti8/intti8 p133/intcp83 p132/intcp82 p131/intcp81 p130/intcp80 v ss v dd p07/intp6 p06/intp5/rtptrg0 p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p157/rtp17 p156/rtp16 p12/sck0/scl0 note 2 p13/si1/rxd0 p14/so1/txd0 p15/sck1/asck0 p20/si2/sda1 note 2 p21/so2 p22/sck2/scl1 note 2 p23/si3/rxd1 p24/so3/txd1 p25/sck3/asck1 p26/ti2/to2 p27/ti3/to3 v dd v ss p30/ti000 p31/ti001 p32/ti010 p33/ti011 p34/to0 p35/to1 p36/ti4/to4 p37/ti5/to5 p120/si4 p121/so4 p122/sck4 p123/clo p124/ti6/to6 p125/ti7/to7 p126/ti10/to10 p127/ti11/to11 p180 p181 p182 p183 p184 p185 p186 p187 v dd v ss p190 p191 p192 p193 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 p194 p195 p196 p197 p170/kr0 p171/kr1 p172/kr2 p173/kr3 p174/kr4 p175/kr5 p176/kr6 p177/kr7 p160/pwm0 p161/pwm1 p162/pwm2 p163/pwm3 p164/csyncin p165/vsout p166/hsout0 p167/hsout1 ic note 1 reset xt1 xt2 v dd x2 x1 v ss p100/rtp00 p101/rtp01 p102/rtp02 p103/rtp03 p104/rtp04 p105/rtp05 p106/rtp06 p107/rtp07 v dd v ss p150/rtp10 p151/rtp11 p152/rtp12 p153/rtp13 p154/rtp14 p155/rtp15 p11/so0 p10/si0/sda0 note 2 p113 p112 p111 p110 wait clkout p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 p96/hldrq p95/hldak p94/astb p93/dstb/rd p92/r/w/wrh p91/uben p90/lben/wrl v ss v dd av dd av ss av ref 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 notes 1. connect directly to v ss. 2. scl0, scl1, sda0, and sda1 are valid for the m pd703039y, 703040y, and 703041y only.
preliminary data sheet u13953ej1v0ds00 4 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y pin identification a16 to a21: address bus ad0 to ad15: address/data bus adtrg: ad trigger input ani0 to ani15: analog input asck0, asck1: asynchronous serial clock astb: address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground bv dd : bus interface power supply bv ss : bus interface ground clkout: clock output clo: clock output (divided) csyncin: csync input dstb: data strobe hldak: hold acknowledge hldrq: hold request hsout0, hsout1: hsync output ic: internally connected intcp80 to intpc83,: interrupt request from peri pherals intcp90 to intcp93, intp0 to intp6, inttclr8, intti8, intti9 kr0 to kr7: key return lben: lower byte enable nmi: non-maskable interrupt request p00 to p07: port 0 p10 to p15: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p65: port 6 p70 to p77: port 7 p80 to p87: port 8 p90 to p96: port 9 p100 to p107: port 10 p110 to p113: port 11 p120 to p127: port 12 p130 to p137: port 13 p140 to p147: port 14 p150 to p157: port 15 p160 to p167: port 16 p170 to p177: port 17 p180 to p187: port 18 p190 to p197: port 19 pwm0 to pwm3: pulse width modulation rd: read reset: reset rtp00 to rtp07,: real-time output port rtp10 to rtp17 rtptrg0, rtptrg1: rtp trigger input r/w: read/write status rxd0, rxd1: receive data sck0 to sck4: serial clock scl0, scl1: serial clock sda0, sda1: serial data si0 to si4: serial input so0 to so4: serial output tclr8: timer clear ti000, ti001, ti010,: timer input ti011, ti2 to ti11 to0 to to7, to80,: timer output to81, to10, to11 txd0,txd1: transmit data uben: upper byte enable v dd : power supply vsout: vsync output v ss : ground wait: wait wrh: write strobe high level data wrl: write strobe low level data x1, x2: crystal for main system clock xt1, xt2: crystal for subsystem clock
preliminary data sheet u13953ej1v0ds00 5 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y internal block diagram notes 1. m pd703039, 703039y, 703040, 703040y: 256 kb m pd703041, 703041y: 192 kb 2. m pd703039, 703039y, 703041, 703041y: 8 kb m pd703040, 703040y: 16 kb 3. sda0, sda1, scl0, and scl1 are valid for the m pd703039y, 703040y, and 703041y only. 4. the i 2 c function is valid for the m pd703039y, 703040y, and 703041y only. intc rom cpu bcu alu pc 32-bit barrel shifter rom correction multiplier 16 16 ? 32 instruction queue system register general registers 32 bits 32 ram hldrq hldak astb dstb/rd r/w/wrh uben lben/wrl wait a16 to a21 ad0 to ad15 nmi intp0 to intp6 csyncin kr0 to kr7 pwm0 to pwm3 so0 si0/sda0 note 3 sck0/scl0 note 3 so2 si2/sda1 note 3 sck2/scl1 note 3 so1/txd0 si1/rxd0 sck1/asck0 so3/txd1 si3/rxd1 sck3/asck1 so4 si4 sck4 to0, to1 tclr8 to80, to81 ti8, ti9 ti000, ti001, ti010, ti011 hsout0, hsout1, vsout ti2/to2, ti3/to3 ti4/to4, ti5/to5 ti6/to6, ti7/to7 ti10/to10, ti11/to11 clkout clo x1 x2 xt1 xt2 reset v dd v ss bv dd bv ss ic ports watch timer rtp rtp00 to rtp07, rtp10 to rtp17 rtptrg0, rtptrg1 watchdog timer a/d converter note 1 note 2 sio cg csi0/i 2 c0 note 4 csi2/i 2 c1 note 4 csi1/uart0 csi3/uart1 variable length csi4 key return function dmac: 6 ch pwm vsync/hsync timer/counter 16-bit timers : tm0, tm1 8-bit timers : tm2 to tm7, tm10, tm11 24-bit timers : tm8, tm9 p190 to p197 p180 to p187 p170 to p177 p160 to p167 p150 to p157 p140 to p147 p130 to p137 p120 to p127 p110 to p113 p100 to p107 p90 to p96 p80 to p87 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 av dd av ref av ss ani0 to ani15 adtrg intcp80 to intcp83, intcp90 to intcp93 inttclr8 intti8, intti9
6 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y contents 1. pin functions ............................................................................................................... ................... 7 1.1 port pins .................................................................................................................. .................................. 7 1.2 non-port pins............................................................................................................... ............................ 11 1.3 pin i/o circuits, i/o buffer supply, and recommended connection of unused pins ....................... 14 2. electrical specifications................................................................................................... ... 18 3. package drawing ............................................................................................................. .......... 37 4. recommended soldering conditions................................................................................ 38
preliminary data sheet u13953ej1v0ds00 7 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 1. pin functions 1.1 port pins (1/4) pin name i/o pull function alternate function p00 nmi p01 intp0 p02 intp1 p03 intp2 p04 intp3 p05 intp4/adtrg p06 intp5/rtptrg0 p07 i/o yes port 0 8-bit i/o port input/output mode can be specified in 1-bit units. intp6 p10 si0/sda0 p11 so0 p12 sck0/scl0 p13 si1/rxd0 p14 so1/txd0 p15 i/o yes port 1 6-bit i/o port input/output mode can be specified in 1-bit units. sck1/asck0 p20 si2/sda1 p21 so2 p22 sck2/scl1 p23 si3/rxd1 p24 so3/txd1 p25 sck3/asck1 p26 ti2/to2 p27 i/o yes port 2 8-bit i/o port input/output mode can be specified in 1-bit units. ti3/to3 p30 ti000 p31 ti001 p32 ti010 p33 ti011 p34 to0 p35 to1 p36 ti4/to4 p37 i/o yes port 3 8-bit i/o port input/output mode can be specified in 1-bit units. ti5/to5 p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 i/o no port 4 8-bit i/o port input/output mode can be specified in 1-bit units. ad4 remark pull: on-chip pull-up resistor
8 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y (2/4) pin name i/o pull function alternate function p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output mode can be specified in 1-bit units. ad7 p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output mode can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output mode can be specified in 1-bit units. a21 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 ani11 p84 ani12 p85 ani13 p86 ani14 p87 input no port 8 8-bit input port ani15 p90 lben/wrl p91 uben p92 r/w/wrh p93 i/o no port 9 7-bit i/o port input/output mode can be specified in 1-bit units. dstb/rd remark pull: on-chip pull-up resistor
preliminary data sheet u13953ej1v0ds00 9 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y (3/4) pin name i/o pull function alternate function p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output mode can be specified in 1-bit units. hldrq p100 rtp00 p101 rtp01 p102 rtp02 p103 rtp03 p104 rtp04 p105 rtp05 p106 rtp06 p107 i/o yes port 10 8-bit i/o port input/output mode can be specified in 1-bit units. rtp07 p110 C p111 C p112 C p113 i/o no port 11 4-bit i/o port input/output mode can be specified in 1-bit units. C p120 si4 p121 so4 p122 sck4 p123 clo p124 ti6/to6 p125 ti7/to7 p126 ti10/to10 p127 i/o no port 12 8-bit i/o port input/output mode can be specified in 1-bit units. ti11/to11 p130 intcp80 p131 intcp81 p132 intcp82 p133 intcp83 p134 ti8/intti8 p135 tclr8/inttclr8 p136 to80 p137 i/o no port 13 8-bit i/o port input/output mode can be specified in 1-bit units. to81 p140 intcp90 p141 intcp91 p142 intcp92 p143 intcp93 p144 ti9/intti9 p145 rtptrg1 p146 C p147 i/o no port 14 8-bit i/o port input/output mode can be specified in 1-bit units. C remark pull: on-chip pull-up resistor
10 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y (4/4) pin name i/o pull function alternate function p150 rtp10 p151 rtp11 p152 rtp12 p153 rtp13 p154 rtp14 p155 rtp15 p156 rtp16 p157 i/o no port 15 8-bit i/o port input/output mode can be specified in 1-bit units. rtp17 p160 pwm0 p161 pwm1 p162 pwm2 p163 pwm3 p164 csyncin p165 vsout p166 hsout0 p167 i/o no port 16 8-bit i/o port input/output mode can be specified in 1-bit units. hsout1 p170 kr0 p171 kr1 p172 kr2 p173 kr3 p174 kr4 p175 kr5 p176 kr6 p177 i/o yes port 17 8-bit i/o port input/output mode can be specified in 1-bit units. kr7 p180 C p181 C p182 C p183 C p184 C p185 C p186 C p187 i/o no port 18 8-bit i/o port input/output mode can be specified in 1-bit units. C p190 C p191 C p192 C p193 C p194 C p195 C p196 C p197 i/o no port 19 8-bit i/o port input/output mode can be specified in 1-bit units. C remark pull: on-chip pull-up resistor
preliminary data sheet u13953ej1v0ds00 11 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 1.2 non-port pins (1/3) pin name i/o pull function alternate function a16 to a21 output no address bus 16 to 21 p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no address/data multiplexed bus 0 to 15 p50 to p57 adtrg input yes a/d converter external trigger input p05/intp4 ani0 to ani7 input no p70 to p77 ani8 to ani15 input no analog input to a/d converter p80 to p87 asck0 p15/sck1 asck1 input yes baud rate clock input for uart0 and uart1 p25/sck3 astb output no external address strobe signal output p94 av dd C C positive power supply for a/d converter and ports used for alternate functions C av ref input C reference voltage input for a/d converter C av ss C C ground potential for a/d converter and ports used for alternate functions C bv dd C C positive power supply for bus interface and ports used for alternate functions C bv ss C C ground potential for bus interface and ports used for alternate functions C clkout output C internal system clock output C clo output no clo output signal p123 csyncin input no csync signal input p164 dstb output no external data strobe signal output p93/rd hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 hsout0 hsync signal output before revision p166 hsout1 output no hsync signal output after revision p167 ic C C internal connection (connect directly to v ss )C intcp80 to intcp83 input no external capture input for cc80 to cc83 p130 to p133 intcp90 to intcp93 input no external capture input for cp90 to cp93 p140 to p143 intp0 to intp3 external interrupt request input (digital noise elimination) p01 to p04 intp4 p05/adtrg intp5 external interrupt request input (digital noise elimination) p06/rtptrg0 intp6 input yes external interrupt request input (digital noise elimination supporting remote controller) p07 remark pull: on-chip pull-up resistor
12 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y (2/3) pin name i/o pull function alternate function inttclr8 input no p135/tclr8 intti8 p134/ti8 intti9 input no external interrupt request input (digital noise elimination) p144/ti9 kr0 to kr7 input yes key return input p170 to p177 lben output no lower byte enable signal output for external data bus p90/wrl nmi input yes non-maskable interrupt request input p00 pwm0 to pwm3 output no output of pwm channels 0 to 3 p160 to p163 rd output no bus read strobe signal output p93/dstb reset input C system reset input C rtp00 to rtp07 p100 to p107 rtp10 to rtp17 output yes real-time output port p150 to p157 rtptrg0 yes p06 rtptrg1 input no rtp external trigger input p146 r/w output no external read/write status output p92/wrh rxd0 p13/si1 rxd1 input yes serial receive data input for uart0 and uart1 p23/si3 sck0 p12/scl0 sck1 p15/asck0 sck2 p22/scl1 sck3 yes serial clock i/o for csi0 to csi3 (3-wire mode) p25/asck1 sck4 i/o no variable-length csi4 serial clock i/o p122 scl0 p12/sck0 scl1 i/o yes serial clock i/o for i 2 c0 and i 2 c1 ( m pd703039y, 703040y and 703041y) p22/sck2 sda0 p10/si0 sda1 i/o yes serial transmit/receive data i/o for i 2 c0 and i 2 c1 ( m pd703039y, 703040y and 703041y) p20/si2 si0 p10/sda0 si1 p13/rxd0 si2 p20/sda1 si3 yes serial receive data input for csi0 to csi3 (3-wire mode) p23/rxd1 si4 input no variable-length csi4 serial receive data input (3-wire mode) p120 so0 p11 so1 p14/txd0 so2 p21 so3 yes serial transmit data output for csi0 to csi3 p24/txd1 so4 output no variable-length csi4 serial transmit data output p121 tclr8 input no external clear input for tm8 p135/inttclr8 ti000 input yes external count clock input/external capture trigger input for tm0 p30 remark pull: on-chip pull-up resistor
preliminary data sheet u13953ej1v0ds00 13 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y (3/3) pin name i/o pull function alternate function ti001 external capture trigger input for tm0 p31 ti010 external count clock input/external capture trigger input for tm1 p32 ti011 external capture trigger input for tm1 p33 ti2 external count clock input for tm2 p26/to2 ti3 external count clock input for tm3 p27/to3 ti4 external count clock input for tm4 p36/to4/a15 ti5 yes external count clock input for tm5 p37/to5 ti6 external count clock input for tm6 p124/to6 ti7 external count clock input for tm7 p125/to7 ti8 external count clock input for tm8 p134/intti8 ti9 external count clock input for tm9 p144/intti9 ti10 external count clock input for tm10 p126/to10 ti11 input no external count clock input for tm11 p127/to11 to0 pulse signal output for tm0 p34 to1 pulse signal output for tm1 p35 to2 pulse signal output for tm2 p26/ti2 to3 pulse signal output for tm3 p27/ti3 to4 pulse signal output for tm4 p36/ti4 to5 yes pulse signal output for tm5 p37/ti5 to6 pulse signal output for tm6 p124/ti6 to7 pulse signal output for tm7 p125/ti7 to80 pulse signal output 0 for tm8 p136 to81 pulse signal output 1 for tm8 p137 to10 pulse signal output for tm10 p126/ti10 to11 output no pulse signal output for tm11 p127/ti11 txd0 p14/so1 txd1 output yes serial transmit data output for uart0 and uart1 p24/so3 uben output no higher byte enable signal output for external data bus p91 v dd C C positive power supply pin C vsout output no vsync signal output p165 v ss C C ground potential C wait input no external wait signal input C wrh higher byte write strobe signal output for external data bus p92/r/w wrl output no lower byte write strobe signal output for external data bus p90/lben x1 input C x2 C no resonator connection for main system clock C xt1 input C xt2 C no resonator connection for sub system clock C remark pull: on-chip pull-up resistor
14 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 1.3 pin i/o circuits, i/o buffer supply, and recommended connection of unused pins table 1-1 shows the i/o circuit type of each pin and the recommended connection of unused pins. for the input/output configuration of each type, refer to figure 1-1. table 1-1. types of pin i/o circuit and recommended connection of unused pins (1/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection method p00 nmi p01 to p04 intp0 to intp3 p05 intp4/adtrg p06 intp5/rtptrg0 p07 intp6 5-w v dd p10 si0/sda0 10-f p11 so0 10-e p12 sck0/scl0 10-f p13 si1/rxd0 5-w p14 so1/txd0 10-e p15 sck1/asck0 10-f v dd p20 si2/sda1 10-f p21 so2 10-e p22 sck2/scl1 10-f p23 si3/rxd1 5-w p24 so3/txd1 10-e p25 sck3/asck1 10-f p26, p27 ti2/to2, ti3/to3 5-w v dd p30, p31 ti000, ti001 p32, p33 ti010, ti011 5-w p34, p35 to0, to1 5-a p36 ti4/to4 p37 ti5/to5 5-w v dd input: independently connect to v dd or v ss via a resistor output: leave open p40 to p47 ad0 to ad7 5 bv dd p50 to p57 ad8 to ad15 5 bv dd p60 to p65 a16 to a21 5 bv dd input: independently connect to bv dd or bv ss via a resistor output: leave open p70 to p77 ani0 to ani7 9 av dd p80 to p87 ani8 to ani15 9 av dd connect to av ss p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 hldrq 5bv dd input: independently connect to bv dd or bv ss via a resistor output: leave open p100 to p107 rtp00 to rtp07 10-e v dd p110 to p113 C 5 v dd p120 si4 5-k v dd input: independently connect to v dd or v ss via a resistor output: leave open
preliminary data sheet u13953ej1v0ds00 15 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y table 1-1. types of pin i/o circuit and recommended connection of unused pins (2/2) pin alternate function i/o circuit type i/o buffer power supply recommended connection method p121 so4 10-g p122 sck4 10-h p123 clo 5 p124 ti6/to6 p125 ti7/to7 p126 ti10/to10 p127 ti11/to11 5-k v dd p130 to p133 intcp80 to intcp83 p134 ti8/intti8 p135 tclr8/inttclr8 5-k p136, p137 to80, to81 5 v dd p140 to p143 intcp90 to intcp93 p144 ti9/intti9 p145 rtptrg1 5-k p146, p147 C 5 v dd p150 to p157 rtp10 to rtp17 5 v dd p160 to p163 pwm0 to pwm3 5 p164 csyncin 5-k p165 vsout p166 hsout0 p167 hsout1 5 v dd p170 to p177 kr0 to kr7 5-k v dd p180 to p187 C 5 v dd p190 to p197 C 5 v dd input: independently connect to v dd or v ss via a resistor output: leave open clkout C 4 bv dd leave open wait C 1 bv dd connect to v dd via a resistor reset C 2 v dd C x1 C C v dd C x2 C C v dd leave open xt1 C C v dd connect to v ss xt2 C C v dd leave open av ref C C C connect to av ss ic C C C connect directly to v ss v dd CCC C v ss CCC C av dd C C C connect to v dd av ss C C C connect to v ss bv dd C C C connect to v dd bv ss C C C connect to v ss
16 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y figure 1-1. pin input/output circuits (1/2) type 1 type 5 type 2 type 5-a type 4 type 5-k schmitt-triggered input with hysteresis characteristics push-pull output that can be set for high impedance output (both p-ch and n-ch are off) in data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable data output disable p-ch out v dd n-ch in p-ch v dd n-ch
preliminary data sheet u13953ej1v0ds00 17 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y figure 1-1. pin input/output circuits (2/2) type 5-w type 10-f type 9 type 10-g type 10-e type 10-h data output disable open drain p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable data output disable open p-ch in/out v dd n-ch input enable p-ch v dd pullup enable data output disable open p-ch in/out v dd n-ch input enable p-ch v dd pullup enable in input enable comparator + C v ref (threshold voltage) p-ch n-ch data output disable input enable open drain p-ch in/out v dd n-ch
18 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 2. electrical specifications absolute maximum ratings (t a = 25c, v ss = 0 v) parameter symbol conditions ratings unit v dd C0.5 to +4.6 v av dd C0.5 to +4.6 v bv dd C0.5 to +4.6 v av ss C0.5 to +0.5 v supply voltage bv ss C0.5 to +0.5 v v i1 note 1 (v dd ) C0.5 to v dd + 0.5 note 4 v input voltage v i2 note 2 (bv dd ) C0.5 to bv dd + 0.5 note 4 v clock input voltage v k x1, xt1, v dd = 2.7 to 3.6 v C0.5 to v dd + 1.0 note 4 analog input voltage v ian note 3 (av dd ) C0.5 to av dd + 0.5 note 4 v analog reference input voltage av ref av ref pin C0.5 to av dd + 0.5 note 4 v per pin 4.0 ma total for p00 to p07, p150 to p157 25 ma total for p100 to p107, p160 to p167 25 ma total for p170 to p177, p190 to p197 25 ma total for p124 to p127, p180 to p187 25 ma total for p30 to p37, p120 to p123 25 ma total for p12 to p15, p20 to p27, p110 to p113 25 ma total for p50 to p57, p60 to p65, clkout 25 ma total for p40 to p47, p90 to p96 25 ma output current, low i ol total for p130 to p137, p140 to p147 25 ma per pin C4.0 ma total for p00 to p07, p150 to p157 C25 ma total for p100 to p107, p160 to p167 C25 ma total for p170 to p177, p190 to p197 C25 ma total for p124 to p127, p180 to p187 C25 ma total for p30 to p37, p120 to p123 C25 ma total for p12 to p15, p20 to p27, p110 to p113 C25 ma total for p50 to p57, p60 to p65, clkout C25 ma total for p40 to p47, p90 to p96 C25 ma output current, high i oh total for p130 to p137, p140 to p147 C25 ma v o1 note 1 (v dd ) C0.5 to v dd + 0.5 v output voltage v o2 note 2 (bv dd ) C0.5 to bv dd + 0.5 v operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c notes 1. ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, reset (includes alternate function pins) 2. ports 4, 5, 6, 9, clkout, wait (includes alternate function pins)
preliminary data sheet u13953ej1v0ds00 19 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 3. ports 7, 8 (includes alternate function pins) 4. be sure not to exceed each absolute maximum rating (max.). cautions 1. do not directly connect to each other output pins (or i/o pins) of ic products, and do not connect them directly to v dd , v cc , or gnd. however, open-drain pins and open-connector pins can be directly connected to each other. moreover, external circuits that implement a timing that avoids conflict with the output of pins that go into high-impedance can be directly connected. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. capacitance (t a = 25c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v 15 pf operating conditions (1) cpu operation frequency parameter symbol conditions min. typ. max. unit @ main system clock operation 0.5 16 mhz cpu operation frequency f cpu @ subsystem clock operation 32.768 mhz (2) supply voltage parameter symbol conditions min. typ. max. unit v dd 2.7 3.6 v av dd 2.7 3.6 v supply voltage bv dd 2.7 3.6 v (3) operation frequency for each supply voltage internal operation clock frequency supply voltage (v dd = av dd = bv dd ) 4 mhz f xx 16 mhz 2.7 to 3.6 v f xt = 32.768 khz 2.7 to 3.6 v
20 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y recommended oscillator (1) main system clock oscillator (t a = - - - - 40 to +85 c) parameter symbol conditions min. typ. max. unit oscillation frequency f xx 416mhz after reset release 2 19 /f xx s oscillation stabilization time after stop mode release note s note values vary depending on the settings of the oscillation stabilization time selection register (osts). remarks 1. place the oscillator as close as possible to x1 and x2. 2. do not wire other signal lines within the broken lines. 3. for resonator selection and oscillation constants, customers are advised to either evaluate the oscillation themselves, or apply to the resonator manufacturer for evaluation. (2) subsystem clock oscillator (t a = - - - - 40 to +85 c) parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32 32.768 35 khz oscillation stabilization time 10 s remarks 1. place the oscillator as close as possible to xt1 and xt2. 2. do not wire other signal lines within the broken lines. 3. for resonator selection and oscillation constants, customers are advised to either evaluate the oscillation themselves, or apply to the resonator manufacturer for evaluation. xt1 xt2 x2 x1
preliminary data sheet u13953ej1v0ds00 21 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y dc characteristics (t a = ?40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol conditions min. typ. max. unit v ih1 pins in note 1 , wait 0.7bv dd bv dd v v ih2 pins in note 2 0.7v dd v dd v v ih3 pins in note 3 , reset 0.75v dd v dd v v ih4 pins in note 4 0.7av dd av dd v input voltage, high v ih5 x, xt1, xt2 0.8v dd v dd v v il1 pins in note 1 , wait bv ss C 0.5 0.3bv dd v v il2 pins in note 2 v ss C 0.5 0.3v dd v v il3 pins in note 3 , reset v ss C 0.5 0.3v dd v v il4 pins in note 4 av ss C 0.5 0.3av dd v input voltage, low v il5 x, xt1, xt2 v ss 0.2v dd v v oh1 note 1 , clkout ioh = C3 ma 0.8bv dd v output voltage, high v oh2 notes 2, 3 ioh = C1 ma 0.8v dd v v ol1 note 1 , clkout iol = 1.6 ma 0.4 v v ol2 notes 2, 3 (except p10, 12, 20, 22) iol = 1.6 ma 0.4 v output voltage, low v ol3 p10, 12, 20, 22 iol = 3 ma 0.4 v i lih1 other than x1, xt1, xt2 5 m a input leakage current, high i lih2 v i = v dd = av dd = bv dd x1, xt1, xt2 20 m a i lil1 other than x1, xt1, xt2 C5 m a input leakage current, low i lil2 v i = 0 v x1, xt1, xt2 C20 m a output leakage current, high i loh v o = v dd = av dd = bv dd 5 m a output leakage current, low i lol v o = 0 v C5 m a supply current note 5 i dd1 normal operation mode (f xx = 16 mhz) 25 55 ma i dd2 halt mode (f xx = 16 mhz) 14 30 ma i dd3 idle mode (f xx = 16 mhz) 1.2 4 ma stop mode (subsystem clock operation: f xt = 32.768 khz, watch timer operation) 10 70 m a i dd4 stop mode (subsystem clock stopped) 1 60 m a pull-up resistor r l 10 30 100 k w notes 1. ports 4, 5, 6, 9 (includes alternate-function pins) 2. p11, p14, p21, p24, p34, p35, p100 to p107, p110 to p113, p121, p123, p136, p137, p146, p147, p150 to p157, p160 to p163, p165 to p167, p180 to p187, p190 to p197 (includes alternate-function pins) 3. p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, p120, p122, p124 to p127, p130 to p135, p140 to p145, p164, p170 to p177 (includes alternate-function pins) 4. ports 7, 8 (includes alternate-function pins) 5. the typical values listed are those of at v dd = 3.3 v. the current that is consumed at output buffers is not included.
22 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y data retention characteristics (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.8 3.6 v data retention current i dddr v dddr [v] 1 60 m a supply voltage rising time t rvd 200 m s supply voltage falling time t fvd 200 m s supply voltage hold time (from stop mode setting) t hvd 0ms stop release signal input time t drel 0ms data retention high-level input voltage v ihdr all input port v ihn v dddr v data retention low-level input voltage v ildr all input port 0 v iln v remark n = 1 to 5 caution be sure to shift to and return from stop mode when v dd is 2.7 v or higher. v dd setting stop mode t hvd t fvd reset (input) nmi, intp0 to intp3 (input) stop release interrupt (nmi, etc.) (when stop mode is released at rising edge) t rvd t drel v dddr v ihdr v ildr v ihdr
preliminary data sheet u13953ej1v0ds00 23 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y ac characteristics ac test input waveforms (v dd , bv dd , av dd ) v dd 0 v v ih v il v ih v il test points ac test output test point (bv dd ) v oh v ol v oh v ol test points load conditions c l = 50 pf dut (device under test) caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
24 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y clock timing operating conditions (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit x1 input cycle 62.5 250 ns xt1 input cycle t cyx <1> 28.6 31.2 m s x1 input high-level width 31.2 125 ns xt1 input high-level width t wxh <2> 14.3 15.6 m s x1 input low-level width 31.2 125 ns xt1 input low-level width t wxl <3> 14.3 15.6 m s x1 input rise time t xr <4> (<1> ? <2> ? <3>)/2 ns x1 input fall time t xf <5> (<1> ? <2> ? <3>)/2 ns clkout output cycle t cyk <6> 62.5 ns 31.2 m s clkout high-level width t wkh <7> 0.4(t ? 20) ns clkout low-level width t wkl <8> 0.4(t ? 20) ns clkout rise time t kr <9> 10 ns clkout fall time t kf <10> 10 ns remark t = t cyk clock timing timing of pins other than x1 and clkout pins (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol condition min. max. unit output rise time t or 20 ns output fall time t of 20 ns x1, xt1 (input) clkout (output) <2> <4> <5> <1> <3> <7> <9> <10> <8> <6>
preliminary data sheet u13953ej1v0ds00 25 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y bus timing (clkout asynchronous) (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit address setup time (to astb )t sast <11> 0.5t ? 20 ns address hold time (from astb )t hsta <12> 0.5t ? 15 ns address float from dstb t fda <13> 2 ns data input setup time from address t daid <14> (2 + n)t ? 30 ns data input setup time from dstb t ddid <15> (1 + n)t ? 30 ns dstb delay time from astb t dstd <16> 0.5t ? 15 ns data input hold time (from dstb - )t hdid <17> 0 ns address output time from dstb - t dda <18> (1 + i)t ? 15 ns astb - delay time from dstb - t ddst1 <19> 0.5t ? 15 ns astb delay time from dstb - t ddst2 <20> (1.5 + i)t ? 15 ns dstb low-level width t wdl <21> (1 + n)t ? 15 ns astb high-level width t wsth <22> t ? 15 ns data output time from dstb t ddod <23> 15 ns data output setup time (to dstb - )t sodd <24> (1 + n)t ? 20 ns data output hold time (from dstb - )t hdod <25> t ? 15 ns t sawt1 <26> 1.5t ? 30 ns wait setup time (to address) t sawt2 <27> n 3 1 (1.5 + n)t ? 30 ns t hawt1 <28> (0.5 + n)t ns wait hold time (from address) t hawt2 <29> n 3 1 (1.5 + n)t ns t sstwt1 <30> 1.5t ? 25 ns wait setup time (to astb ) t sstwt2 <31> n 3 1 (1.5 + n)t ? 25 ns t hstwt1 <32> nt + 5 ns wait hold time (from astb ) t hstwt2 <33> n 3 1 (1 + n)t + 5 ns hldrq high-level width t whqh <34> t + 10 ns hldak low-level width t whal <35> t ? 15 ns bus output delay time from hldak - t dhac <36> 0 ns hldak delay time from hldrq t dhqha1 <37> 1.5t (2n + 7.5)t + 25 ns hldak - delay time from hldrq - t dhqha2 <38> 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in the bus cycle. sampling timing changes when a programmable wait is inserted. 3. i: number of idle states inserted after the read cycle (0 or 1). 4. the specifications described above are the values of when a clock of duty ratio 1:1 is input from x1.
26 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y bus timing (clkout synchronous) (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit address delay time from clkout - t dka <39> 0 19 ns address float delay time from clkout - t fka <40> ?12 7 ns astb delay time from clkout t dkst <41> ?12 7 ns dstb - delay time from clkout - t dkd <42> ?5 14 ns data input setup time (to clkout - )t sidk <43> 15 ns data input hold time (from clkout - )t hkid <44> 5 ns data output delay time from clkout - t dkod <45> 19 ns wait setup time (to clkout )t swtk <46> 15 ns wait hold time (from clkout )t hkwt <47> 5 ns hldrq setup time (to clkout )t shqk <48> 15 ns hldrq hold time (from clkout )t hkhq <49> 5 ns address float delay time from clkout - t dkf <50> 19 ns hldak delay time from clkout - t dkha <51> 19 ns remark the specifications described above are the values of when a clock of duty ratio 1:1 is input from x1.
preliminary data sheet u13953ej1v0ds00 27 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y read cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), rd (output) wait (input) t1 t2 tw t3 <39> <40> <41> <11> <42> <19> <18> <20> <16> <30> <46> <32> <31> <33> <26> <28> <27> <29> <47> <46> <47> <15> <21> <17> <41> <14> <43> <44> address hi-z <13> <42> <12> <22> note r/w (output), uben (output), lben (output) remark wrl and wrh are high level. data
28 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y write cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), wrl (output), wrh (output) wait (input) t1 t2 tw t3 <39> <45> <41> <11> <42> <19> <25> <16> <30> <46> <32> <31> <33> <26> <28> <27> <29> <47> <46> <47> <24> <21> <22> <12> <41> data address <23> <42> note r/w (output), uben (output), lben (output) remark rd is high level.
preliminary data sheet u13953ej1v0ds00 29 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y bus hold clkout (output) hldrq (input) hldak (output) a16 to a21 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), rd (output), wrl (output), wrh (output) <48> <49> <51> <50> <36> <35> <37> <38> <48> <51> <34> th th th ti hi-z hi-z hi-z data hi-z note r/w (output), uben (output), lben (output)
30 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y reset/interrupt timing (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit reset high-level width t wrsh <52> 500 ns reset low-level width t wrsl <53> 500 ns nmi high-level width t wnih <54> 500 ns nmi low-level width t wnil <55> 500 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn high-level width t with <56> n = 6, digital noise elimination 3tsmp + 20 ns n = 0 to 3, analog noise elimination 500 ns n = 4, 5, digital noise elimination 3t + 20 ns intpn low-level width t witl <57> n = 6, digital noise elimination 3tsmp + 20 ns remarks 1. t = 1/f xx 2. tsmp = noise elimination sampling clock frequency reset interrupt <52> <53> reset (input) <54> <55> nmi (input) <56> <57> intpn (input) remark n = 0 to 6
preliminary data sheet u13953ej1v0ds00 31 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y tin input timing (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit tin0, tin1 (n = 00, 01) high-level width 2t sam + 20 note ns tin (n = 2 to 7, 10, 11) high-level width t tih <58> 3/f xx + 20 ns tin0, tin1 (n = 00, 01) low-level width 2t sam + 20 note ns tin (n = 2 to 7, 10, 11) low-level width t til <59> 3/f xx + 20 ns note t sam can be selected by setting the prmn1 and prmn0 bits of prescaler mode registers n0, n1 (prmn0, prmn1) (n = 0, 1). tm0 (prm00, prm01 registers): t sam = 2/f xx , 4/f xx , 16/f xx , 64/f xx , 256/f xx , 1/intwti period tm1 (prm10, prm11 registers): t sam = 2/f xx , 4/f xx , 16/f xx , 32/f xx , 128/f xx , 256/f xx however, when the tin0 valid edge is selected as the count clock, t sam = 4/f xx (n = 0, 1). remark n = 000, 001, 010, 011, 10, 11, 2 to 7 tin <58> <59>
32 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 3-wire sio timing (1) master mode (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit sckn cycle time t kcy1 <60> 400 ns sckn high-level width t kh1 <61> 140 ns sckn low-level width t kl1 <62> 140 ns sin setup time (to sckn - )t sik1 <63> 50 ns sin hold time (from sckn )t ksi1 <64> 50 ns son output delay time from sckn t kso1 <65> 60 ns remark n = 0 to 3 (2) slave mode (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit sckn cycle time t kcy2 <60> 400 ns sckn high-level width t kh2 <61> 140 ns sckn low-level width t kl2 <62> 140 ns sin setup time (to sckn - )t sik2 <63> 50 ns sin hold time (from sckn )t ksi2 <64> 50 ns son output delay time from sckn t kso2 <65> 60 ns remark n = 0 to 3 remark n = 0 to 3 sckn (i/o) son (output) sin (input) <60> <61> <62> <63> <64> <65>
preliminary data sheet u13953ej1v0ds00 33 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 3-wire variable-length csi timing (1) master mode (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit sck4 cycle time t kcy1 <66> 400 ns sck4 high-level width t kh1 <67> 140 ns sck4 low-level width t kl1 <68> 140 ns si4 setup time (to sck4 - )t sik1 <69> 50 ns si4 hold time (from sck4 - )t ksi1 <70> 50 ns so4 output delay time from sck4 t kso1 <71> 60 ns (2) slave mode (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit sck4 cycle time t kcy2 <66> 400 ns sck4 high-level width t kh2 <67> 140 ns sck4 low-level width t kl2 <68> 140 ns si4 setup time (to sck4 - )t sik2 <69> 50 ns si4 hold time (from sck4 - )t ksi2 <70> 50 ns so4 output delay time from sck4 t kso2 <71> 60 ns sck4 (i/o) so4 (output) si4 (input) <66> <67> <68> <69> <70> <71>
34 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y uart timing (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) parameter symbol condition min. max. unit asckn cycle time t kcy13 <72> 200 ns asckn high-level width t kh13 <73> 80 ns asckn low-level width t kl13 <74> 80 ns remark n = 0, 1 remark n = 0, 1 <73> <74> <72> asckn (input)
preliminary data sheet u13953ej1v0ds00 35 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y i 2 c bus mode (only for m m m m pd703039y, 703040y, and 703041y) (t a = C40 to +85c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) standard mode high-speed mode parameter symbol min. max. min. max. unit scln clock frequency f clk 0 100 0 400 khz bus free time (between stop and start conditions) t buf <75> 4.7 C 1.3 C m s hold time note 1 t hd : sta <76> 4.0 C 0.6 C m s scln clock low-level width t low <77> 4.7 ? 1.3 ? m s scln clock high-level width t high <78> 4.0 ? 0.6 ? m s setup time of start/restart conditions t su : sta <79> 4.7 ? 0.6 ? m s cbus-compatible master 5.0 ? ? ? m s data hold time i 2 c mode t hd : dat <80> 0 note 2 C 0 note 2 0.9 note 3 m s data setup time t su : dat <81> 250 ? 100 note 4 Cns rising time of sdan and scln signals t r <82> C 1000 20 + 0.1cb note 5 300 ns falling time of sdan and scln signals t f <83> C 300 20 + 0.1cb note 5 300 ns setup time of stop condition t su : sto <84> 4.0 C 0.6 C m s pulse width of spike suppressed by input filter t sp <85> ? ? 0 50 ns load capacitance of bus lines cb ? 400 ? 400 pf notes 1. the first clock pulse in the start condition is generated after the hold time. 2. the system must internally provide at least 300 ns hold time for the sdan signal (at v ihmin. of the scln signal) in order to fill the undefined area that appears at the scln falling edge. 3. if the system does not extend the low hold time (t low ), it is required to satisfy only the maximum data hold time (t hd : dat ). 4. the high-speed i 2 c bus is available in the standard mode i 2 c bus system. in this case, following conditions should be satisfied. when the system does not extend the low-state hold time of the scln signal t su : dat 3 250 ns when the system extends the low-state hold time of the scln signal before the scln line is released (t rmax. + t su : dat = 1000 + 250 = 1250 ns: standard mode i 2 c bus specification), send the next data bit to the sdan line. 5. cb: total capacitance of one bus line (unit: pf) remark n = 0, 1
36 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y i 2 c bus mode (only for m m m m pd703039y, 703040y, and 703041y) remark n = 0, 1 a/d converter (t a = C40 to +85c, v dd = av dd = av ref = 2.7 to 3.6 v, av ss = v ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 0.8 %fsr conversion time t conv 5 100 m s zero-scale error note 1 0.4 %fsr full-scale error note 1 0.4 %fsr integral linearity error note 2 4.0 lsb differential linearity error note 2 4.0 lsb analog reference voltage av ref av ref = av dd 2.7 3.6 v analog input voltage v ian av ss av ref v av ref current ai ref 240 360 m a supply current ai dd 13ma notes 1. excluding quantization error ( 0.05%fsr) 2. excluding quantization error ( 0.5lsb) remark lsb: least significant bit fsr: full scale range scln sdan <83> <75> <81> <80> <79> <78> <76> <85> <84> <82> <77> stop condition start condition stop condition restart condition <76>
preliminary data sheet u13953ej1v0ds00 37 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 3. package drawing 144 176 133 45 88 132 89 s s n 176-pin plastic lqfp (fine pitch) (24x24) j t detail of lead end c d a b r k m i s p l u q g f note each lead centerline is located within 0.10 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 26.0 0.2 24.0 0.2 1.25 26.0 0.2 s176gm-50-ueu c 24.0 0.2 l 0.5 f 1.25 n p q s 0.08 1.4 0.1 0.05 1.5 0.1 m 0.17 + 0.03 - 0.07 h 0.22 0.05 i j k 0.08 0.5 (t.p.) 1.0 0.2 r3 + 4 - 3 m h
38 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y 4. recommended soldering conditions the m pd703039, 703039y, 703040, 703040y, 703041, and 703041y should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales representative. table 4-1. surface mounting type soldering conditions m m m m pd703039gm- -ueu: 176-pin plastic lqfp (fine pitch) (24 24 mm) m m m m pd703040gm- -ueu: 176-pin plastic lqfp (fine pitch) (24 24 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 sec. max. (at 210 c or higher), count: twice or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) ir35-103-2 vps package peak temperature: 215 c, time: 40 sec. max. (at 200 c or higher), count: twice or less, exposure limit: 3 days note (after that, prebake at 125 c for 10 hours) vp15-103-2 partial heating pin temperature: 300 c max., time 3 sec. max. (per pin row) ? note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. cautions 1. do not use different soldering methods together (except for partial heating). 2. soldering conditions for m pd703039y, 703040y, 703041, and 703041y are undetermined.
preliminary data sheet u13953ej1v0ds00 39 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y [memo]
40 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y [memo]
preliminary data sheet u13953ej1v0ds00 41 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y [memo]
42 preliminary data sheet u13953ej1v0ds00 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. related document m pd70f3040, 70f3040y data sheet (u14622e) reference document electrical characteristics for microcomputer (iei-601) note note this document number is that of the japanese version. the documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. v850 family and v850/sv1 are trademarks of nec corporation. notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
preliminary data sheet u13953ej1v0ds00 43 m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j99.1
m m m m pd703039, 703039y, 703040, 703040y, 703041, 703041y the information contained in this document is being issued in advance of the production cycle for the device. the parameters for the device may change before final production or nec corporation, at its own discretion, may withdraw the device prior to its production. ? no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. ? nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, c opyrights or other intellectual property rights of nec corporation or others. ? descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. nec corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. ? while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. ? nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. m5 98. 8 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative.

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